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veripower
AI-assisted IC design flow skills — specification, RTL, lint/CDC, simulation, synthesis, timing analysis, and signoff
README / ZH
插件文档
目录摘要
AI-assisted IC design flow skills — specification, RTL, lint/CDC, simulation, synthesis, timing analysis, and signoff
dsh.pub 核对固定版本的组合包契约、运行时事实与分发语义；完整 README 请查看源仓库。
在 GitHub 阅读完整 README